Speculative data processing operations are a technique used to increase speed of operation. An instruction is issued on speculation before the input operands are confirmed. If the input operands are later found to have been correct, then the speculative execution saved any time between the issue of the speculative instruction and the time when the operands are confirmed as valid. If the operands are later found to be incorrect, then the instruction is issued with the correct operands. This results in no increase in speed, but generally there is no loss of processing due to the speculative execution. Speculative execution is generally only used in super-scalar data processors or very long instruction word (VLIW) data processors which have vacant or empty instruction issue slots that can be filled by the speculative execution. Super-scalar and VLIW data processors have the capability of issuing more than one instruction each machine cycle. The fastest processing operation occurs when these data processors issue their maximum number of instructions each cycle. However, data dependencies, resource conflicts and other issues often prevent issuing the maximum number of instructions. Speculative execution is a technique intended to permit these otherwise unused instruction slots to be profitably employed. As described above, speculative execution employing unused instruction slots has the potential for performance gain and no performance loss.
Data loads generally have the longest latency of any instructions in super-scalar or VLIW data processors. Differences in the speed of operation of high end data processors and large memories can cause length latency in data loads. Thus speculative execution of data loads may be particularly advantageous. The memory address for such a data load is often stored in a data register as an address pointer. The data in the data register is supplied to the memory to specify the address location storing the desired data. Many data processors use a base plus offset address. A base data register stores a base address and an offset data register stores an offset from the base address. The final memory address is the sum of the base address and the offset. Generally the base address is modified infrequently with most of the variability in the offset. The identity of the address register or offset address register must be known at the time of the issue of a data load instruction. A speculative load can be issued using the data in this known address register or offset register at a time before this load is confirmed valid.
There are two types of possible faults of such speculative loads. The data stored in this address register or offset register may not be proper for the intended data load. This would occur if the data in the address register or data register were changed between the time of the issue of the speculative load instruction and the issue of the actual load instruction. It is also possible that the data stored in the intended memory location is incorrect. This would occur if there were a data write to the memory address between the time of the issue of the speculative load instruction and the issue of the actual load instruction. This invention deals only with the invalid address fault.
A speculative load to an invalid address may cause problems. On many data processors, load instructions to bogus addresses can cause a memory access fault. That is, a load instruction specifying an address not implemented in the system causes an operating system fault. With 32-bit data registers capable of specifying more than 4 billion data words, it is likely that not all possible data values that can be stored in an address register or an offset register point to a valid memory address. Such memory access faults may cause the application to crash or require hundreds or thousands of machine cycles for the operating system to recover. The possibility of such memory faults prevents more frequent use of speculative loads.
If such a speculative load can be restricted to a subset of the address space which known to be accessible without faulting, it may be possible to issue a speculative load earlier in the instruction stream. In many cases, program performance could be significantly improved if a speculative load is issued before the address is confirmed valid. Such early data loading may prevent the algorithm from waiting for data following confirmation of the data address.
There are only two known solutions to this problem. The speculative load may use predication to conditionally prevent an improper load from executing. Using predication delays the load unit the predicate is known. The second known solution uses special purpose hardware. Many data processors do not include special purpose hardware for such speculative loads. Accordingly, another method enabling speculative data loads would be useful in data processors.